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Ordering number : ENA1122
LC876D16A LC876D08A
Overview
CMOS IC ROM 16K/8K byte, RAM 1024 byte on-chip
8-bit 1-chip Microcontroller
The SANYO LC876D16A/LC876D08A is 8-bit microcomputer with the following on-chip functional blocks: * CPU: operable at a minimum bus cycle time of 100ns * 16K/8K-byte ROM * On-chip RAM: 1024 byte * VFD automatic display controller/driver * 16-bit timer/counter (can be divided into two 8-bit timers) * Two 8-bit timer with prescaler * Timer for use as date/time clock * Day-Minute-Second Counter (DMSC) * System clock divider function * Synchronous serial I/O port (with automatic block transmit/receive function) * Asynchronous/synchronous serial I/O port * Remote control receive function * 8-channelx8-bit AD converter * 15-source 10-vectored interrupt system All of the above functions are fabricated on a single chip.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
Ver.1.00
52108HKIM 20080215-S00003 No.A1122-1/19
LC876D16A/08A
Features
Read-Only Memory (Mask ROM) * 16384 x 8 bits (LC876D16A) * 8192 x 8 bits (LC876D08A) Random Access Memory (RAM) * 1024 x 9 bits Minimum Bus Cycle Time * 100ns (10MHz) VDD=3.0 to 5.5V Note: The bus cycle time indicates ROM read time. Minimum Instruction Cycle Time (tCYC) * 300ns (10MHz) VDD=3.0 to 5.5V Ports * Input/output ports Data direction programmable for each bit individually: 10 (P1n, P7n) Data direction programmable in nibble units: 8 (P0n) (When N-channel open drain output is selected, data can be input in bit units.) * VFD output ports Large current outputs for digits: 9 (S0/T0 to S8/T8) Large current outputs for digits/segments: 7 (S9/T9 to S15/T15) Digit/segment outputs: 8 (S16 to S23) Segment outputs: 30 (S24 to S53) * Oscillator pins: 2 (CF1/XT1, CF2/XT2) * Reset pin: 1 (RES) * Power supply: 4 (VSS1, VDD1 to VDD3) * VFD power supply: 1 (VP) VFD Automatic Display Controller * Programmable segment/digit output pattern Output can be switched between digit/segment waveform output (pins 9 to 23 can be used for output of digit waveforms). parallel-drive available for large current VFD. * 16-step dimmer function available Timers * Timer 0: 16-bit timer/counter with capture register Mode 0: 2 channel 8-bit timer with programmable 8-bit prescaler and 8-bit capture register Mode 1: 8-bit timer with 8-bit programmable prescaler and 8-bit capture register + 8-bit counter with 8-bit capture register Mode 2: 16-bit timer with 8-bit programmable prescaler and 16-bit capture register Mode 3: 16-bit counter with 16-bit capture register * Timer 4: 8-bit timer with 6-bit prescaler * Timer 5: 8-bit timer with 6-bit prescaler * Base Timer 1) The clock signal can be selected from any of the following. Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0 2) Interrupts can be selected to occur at one of five different times. * Day and time counter 1) Using with a base timer, it can be used as 65000 day + minute + second counter.
No.A1122-2/19
LC876D16A/08A
SIO * SIO 0: 8-bit synchronous serial interface 1) LSB first/MSB first function available 2) Internal 8-bit baud-rate generator (maximum transmit clock period 4/3 tCYC) 3) Consecutive automatic data communication (1 to 256 bits (communication available for each bit) (stop and reopening available for each byte) * SIO 1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial IO (2-wire or 3-wire, transmit clock 2 to 512 tCYC) Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8 to 2048 tCYC) Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tCYC) Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection) AD Converter: 8 bits x 8 channels Remote Control Receiver Circuit (sharing pins with P70/INT0/RMIN) * Noise rejection function (Units of noise rejection filter: about 120s, when selecting a 32.768kHz crystal oscillator as a clock.) * Supporting reception formats with a guide-pulse of half-clock/clock/none. * Determines a end of reception by detecting a no-signal periods (No carrier). (Supports same reception format with a different bit length.) * X'tal HOLD mode release function Watchdog Timer * The watching timer period is set using an external RC. * Watchdog timer can produce interrupt, system reset. Clock Output Function 1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock. 2) Able to output oscillation clock of sub clock. System Clock Divider Function * Able to reduce current consumption Available minimum instruction cycle time: 300ns, 600ns, 1.2s, 2.4s, 4.8s, 9.6s, 19.2s, 38.4s, 76.8s. (Using 10MHz main clock) Interrupts: 15 sources, 10 vectored interrupts * Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or lower priority interrupt request is refused. * If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence. In the case of equal priority levels, the vector with the lowest address takes precedence.
No. 1 2 3 4 5 6 7 8 9 10 Vector 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Selectable Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L SIO0 SIO1 ADC Port0/T4/T5 INT0 INT1 INT2/T0L/remote control receiver INT3/Base timer 0/1 T0H Interrupt Signal
* Priority Level: X>H>L * For equal priority levels, vector with lowest address takes precedence. Subroutine Stack Levels: 512 levels Maximum (Stack is located in RAM.)
No.A1122-3/19
LC876D16A/08A
Multiplication and Division * 16 bits x 8 bits (5 tCYC execution time) * 24 bits x 16 bits (12 tCYC execution time) * 16 bits / 8 bits (8 tCYC execution time) * 24 bits / 16 bits (12 tCYC execution time) Oscillation Circuits * On-chip RC oscillation circuit for system clock use. * On-chip CF oscillation circuit* for system clock use. (Rf built in) * On-chip Crystal oscillation circuit* low speed system clock use. (Rf built in) * Frequency variable RC oscillation circuit (internal) for system clock. 1) Adjustable in 4% (typ) step from a selected center frequency. 2) Measures oscillation clock using a input signal from XT1 as a reference. * The CF oscillation terminal and the crystal oscillation terminal cannot be used at the same time because of commonness. Standby Function * HALT mode HALT mode is used to reduce power consumption. Program execution is stopped. Peripheral circuits still operate but VFD display and some serial transfer operations stop. 1) Oscillation circuits are not stopped automatically. 2) Release occurs on system reset or by interrupt. * HOLD mode HOLD mode is used to reduce power consumption. Both program execution and peripheral circuits are stopped. 1) The CF, RC, X'tal and frequency variable RC oscillators automatically stop operation. 2) Release occurs on any of the following conditions. (1) input to the reset pin goes "Low" (2) a specified level is input to at least one of INT0, INT1, INT2 (3) an interrupt condition arises at port 0 * X'tal HOLD mode. X'tal HOLD mode is used to reduce power consumption. Program execution is stopped. All peripheral circuits except the base-timer are stopped. 1) The CF, RC, frequency variable RC oscillation circuits stop automatically. 2) Crystal oscillator is maintained in its state at HOLD mode inception. 3) Release occurs on any of the following conditions. (1) input to the reset pin goes "Low" (2) Setting at least one of the INT0, INT1 and INT2 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established in the base timer circuit (5) Having an interrupt source established in the remote control receiver circuit Package Form * QFP80(14x14): Lead-free type Development Tools * On-chip debugger: TCB87- type-B + LC87F6D64A
No.A1122-4/19
LC876D16A/08A
Package Dimensions
unit : mm (typ) 3255
17.2 60 61 41 40
80 1 (0.83) 0.65 0.25 20
21 0.15
3.0max
0.1
(2.7)
SANYO : QFP80(14X14)
Pin Assignment
S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 S38 S39 VDD3 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 P10/SO0 P11/SI0/SB0 P12/SCK0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
14.0 17.2
0.8
14.0
P13/SO1 P14/SI1/SB1 P15/SCK1 P16/INT2/T0IN P17/INT3/T0IN RES VSS1 CF1/XT1 CF2/XT2 VDD1 P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/AN5 P06/AN6 P07/AN7 P70/INT0/T0LCP/RMIN P71 INT1/T0HCP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
LC876D16A/08A
S17 S16 VDD2 VP1 S15/T15 S14/T14 S13/T13 S12/T12 S11/T11 S10/T10 S9/T9 S8/T8 S7/T7 S6/T6 S5/T5 S4/T4 S3/T3 S2/T2 S1/T1 S0/T0
Top view
SANYO: QFP80(14x14) "Lead-free Type"
No.A1122-5/19
LC876D16A/08A
System Block Diagram
Interrupt control
IR
PLA
Standby control
ROM
VMRC RC
Clock generator
CF X'tal
PC
SIO0
Bus interface
ACC
SIO1
Port 0
B register
Port 1
C register
Timer 0
ADC ALU
Base timer
Remote control receiver circuit
VFD Controller
DMSC
PSW
Timer 4
INT0 to 3 Noise Rejection Filter
RAR
Timer 5
RAM
Stack pointer
Watchdog timer
No.A1122-6/19
LC876D16A/08A
Pin Description
Pin name VSS1 VDD1 VDD2 VDD3 VP PORT0 P00 to P07 I/O * Power supply (-) * Power supply (+) Function Option No No
I/O
* VFD Power supply (-) * 8bit input/output port * Data direction programmable in nibble units * Use of pull-up resistor can be specified in nibble units * Input for HOLD release * Input for port 0 interrupt * Other functions P04: clock output (system clock/can selected from sub clock) AD input port: AN0 to AN7
No Yes
PORT1 P10 to P17
I/O
* 8bit input/output port * Data direction programmable for each bit * Use of pull-up resistor can be specified for each bit * Other pin functions P10: SIO0 data output P11: SIO0 data input/bus input/output P12: SIO0 clock input/output P13: SIO1 data output P14: SIO1 data input/bus input/output P15: SIO1 clock input/output P16: INT2 P17: INT3/Buzzer output The following types of interrupt detection are possible: Rising INT2 INT3 enable enable Falling enable enable Rising/ Falling enable enable H level disable disable L level disable disable
Yes
PORT7 P70 to P71
* 2bit input/output port * Data direction can be specified for each bit * Use of pull-up resistor can be specified for each bit * Other functions P70: INT0 input/HOLD release input/Timer 0L capture input/ output for watchdog timer/Remote control receiver input P71: INT1 input/HOLD release input/Timer 0H capture input The following types of interrupt detection are possible: Rising INT0 INT1 enable enable Falling enable enable Rising/ Falling disable disable H level enable enable L level enable enable
No
S0/T0 to S8/T8 S9/T9 to S15/T15 S16 to S53 RES CF1/XT1
O O O I I
* Large current output for VFD display controller digit (can be used for segment) * Large current output for VFD display controller segment/digit * Output for VFD display controller segment Reset terminal * Input terminal for ceramic oscillator < crystal oscillator selected> * Input for 32.768kHz crystal oscillation When not in use, connect to VDD1.
No No No No No
CF2/XT2
O
* Output terminal for ceramic oscillator < crystal oscillator selected> * Output for 32.768kHz crystal oscillation When not in use, set to oscillation mode and leave open circuit.
No
No.A1122-7/19
LC876D16A/08A
Port Output Types
Output configuration and pull-up/pull-down resistor options are shown in the following table. Input/output is possible even when port is set to output mode.
Terminal P00 to P07 (Note 1) P10 to P17 each bit Option Selected in Units of each bit Options 1 2 1 2 P70 P71 S0/T0 to S15/T15 S16 to S53 None None None CMOS Nch-open drain CMOS Nch-open drain Nch-open drain CMOS High voltage Pch-open drain Output Format Pull-up Resistor Programmable Programmable Programmable Programmable Programmable Programmable Pull-down Resistor Fixed
Note 1: Programmable pull-up resisters of Port 0 can be attached in nibble units (P00 to P03, P04 to P07). * Note: Connect as follows to reduce noise on VDD and increase the back-up time. VSS1 must be connected together and grounded.
LSI VDD1 Power supply
Back-up capacitors
VDD2 VDD3
VFD powers
VSS1
No.A1122-8/19
LC876D16A/08A
Absolute Maximum Ratings at Ta = 25C, VSS1 = 0V
Parameter Supply voltage Input voltage Symbol VDD max VI(1) VI(2) Output voltage VO(1) VO(2) Input/Output voltage Peak output current IOPH(2) IOPH(3) IOPH(4) Average output current IOMH(2) High level output current IOMH(3) IOMH(4) Total output current IOAH(1) IOAH(2) IOAH(3) IOAH(4) IOAH(5) IOAH(6) IOAH(7) IOAH(8) IOAH(9) IOAH(10) IOAH(11) Peak output Low level output current current Average output current Total output current IOPL(1) IOPL(2) IOPML(1) IOML(2) IOAL(1) IOAL(2) IOAL(3) IOAL(4) Maximum power dissipation Operating temperature range Storage temperature range Tstg -55 +125 Topr -40 +85 C Pd max Port 71 S0/T0 to S15/T15 S16 to S53 Port 0 Port 1 Ports 0, 1 Port 71 S0/T0 to S15/T15 S16 to S33 S0/T0 to S15/T15 S16 to S33 S34 to S39 S40 to S47 S48 to S53 S34 to S53 Ports 0, 1 Port 7 Ports 0, 1 Port 7 Port 0 Port 1 Port 7 Ports 0, 1, 7 QFP80(14x14) Total of all pins Total of all pins Total of all pins Total of all pins Current at each pin Current at each pin Current at each pin Current at each pin Total of all pins Total of all pins Total of all pins Total of all pins Ta=-40 to +85C IOMH(1) Port 71 S0/T0 to S15/T15 S16 to S53 Ports 0, 1 IOPH(1) Ports 0, 1 * CMOS output selected * Current at each pin Current at each pin Current at each pin Current at each pin * CMOS output selected * Current at each pin Current at each pin Current at each pin Current at each pin Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins VIO(1) Pin/Remarks VDD1, VDD2, VDD3 CF1/XT1, RES VP S0/T0 to S15/T15 S16 to S53 CF2/XT2 Ports 0, 1, 7 Conditions VDD[V] VDD1=VDD2=VDD3 min -0.3 -0.3 VDD-45 VDD-45 -0.3 -0.3 -10 -5 -30 -15 -7.5 -3 -15 -10 -30 -30 -30 -5 -60 -60 -60 -60 -60 -60 -60 20 10 15 7.5 50 50 20 80 mW mA Specification typ max +6.5 VDD+0.3 VDD+0.3 VDD+0.3 VDD+0.3 VDD+0.3 V unit
No.A1122-9/19
LC876D16A/08A
Allowable Operating Conditions at Ta = -40C to +85C, VSS1 = 0V
Specification Parameter Operating supply voltage range Hold voltage Pull-down supply voltage Input high voltage VIH(2) VIH(3) Input low voltage VIL(1) Port 70 Watchdog timer XT1/CF1, RES Ports 0, 1 Port 71 Port 70 port input/interrupt VIL(2) VIL(3) Operation cycle time External system clock frequency FEXCF(1) CF1 * CF2 open circuit * system clock divider set to 1/1 * external clock DUTY=505% * CF2 open circuit * system clock divider set to 1/2 * external clock DUTY=505% Oscillation stabilizing time period (Note 2-1) (Note 2-2) FmRC FmVMRC FsX'tal XT1, XT2 FmCF(2) CF1, CF2 FmCF(1) CF1, CF2 * 10MHz ceramic resonator oscillation * Refer to figure 1 * 4MHz ceramic resonator oscillation * Refer to figure 1 RC oscillation Frequency variable RC oscillation circuit 32.768kHz crystal resonator oscillation Refer to figure 2 2.5 to 5.5 32.768 kHz 2.5 to 5.5 2.5 to 5.5 0.3 1.0 4 2.0 2.5 to 5.5 4 MHz 3.0 to 5.5 10 tCYC Port 70 Watchdog timer XT1/CF1, RES Output disable 2.5 to 5.5 2.5 to 5.5 3.0 to 5.5 2.5 to 5.5 3.0 to 5.5 2.5 to 5.5 3.0 to 5.5 2.5 to 5.5 VSS VSS 0.300 0.735 0.1 0.1 0.2 0.2 0.8VDD -1.0 0.25VDD 200 200 10 4 MHz 20 8 s Output disable 2.5 to 5.5 VSS 0.1VDD +0.4 Output disable VIH(1) Ports 0, 1 Output disable 2.5 to 5.5 2.5 to 5.5 2.5 to 5.5 VHD VP VDD1 VP RAM and the register data are kept in HOLD mode. Symbol VDD(1) VDD(2) Pin/Remarks VDD1=VDD2=VDD3 Conditions VDD[V] 0.300stCYC200s 0.735stCYC200s min 3.0 2.5 2.0 -35 0.3VDD +0.7 0.9VDD 0.75VDD typ max 5.5 5.5 5.5 VDD VDD VDD VDD V unit
Note 2-1: The oscillation constant is shown in table 1 and table 2. Note 2-2: The CF oscillation terminal and the crystal oscillation terminal cannot be used at the same time because of commonness.
No.A1122-10/19
LC876D16A/08A
Electrical Characteristics at Ta = -40C to +85C, VSS1 = 0V
Parameter Input high current Symbol IIH(1) Pin/Remarks Ports 0, 1, 7 Conditions VDD[V] * Output disable * Pull-up resister OFF. * VIN=VDD (including OFF state leak current of the output Tr.) IIH(2) IIH(3) Input low current IIL(1) RES CF1/XT1 Ports 0, 1, 7 VIN=VDD VIN=VDD * Output disable * Pull-up resister OFF. * VIN=VSS (including OFF state leak current of the output Tr.) IIL(2) IIL(3) Output high voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) VOH(6) VOH(7) RES CF1/XT1 Port 0: CMOS output option Ports 1 Port 71 S0/T0 to S15/T15 VIN=VSS VIN=VSS IOH=-1.0mA IOH=-0.5mA IOH=-0.1mA IOH=-0.4mA IOH=-20.0mA IOH=-10.0mA * IOH=-1.0mA * IOH at any single pin is not over 1mA. VOH(8) VOH(9) VOH(10) S16 to S53 IOH=-5.0mA IOH=-2.5mA * IOH=-1.0mA * IOH at any single pin is not over 1mA. Output low voltage VOL(1) VOL(2) VOL(3) VOL(4) Pull-up resistor Rpu Port 7 Ports 0, 1, 7 Ports 0, 1 IOL=10mA IOL=5mA IOL=1.6mA IOL=1mA VOH=0.9VDD * Output P-ch Tr. OFF * VOUT=VSS * Output P-ch Tr. OFF * VOUT=VDD-40V Pull-down resistor Rpd * S0/T0 to S15/T15 * S16 to S53 Hysteresis voltage Pin capacitance CP VHYS(1) * Ports 0, 1, 7 * RES All pins * f=1MHz * All other terminals connected to VSS. * Ta=25C 2.5 to 5.5 10 pF * Output P-ch Tr. OFF * VOUT=3V * Vp=-30V 2.5 to 5.5 0.1VDD V 5.0 60 100 200 k 4.5 to 5.5 3.0 to 5.5 2.5 to 5.5 2.5 to 5.5 4.5 to 5.5 2.5 to 4.5 Output off-leak current IOFF(2) IOFF(1) S0/T0 to S15/T15, S16 to S53 2.5 to 5.5 2.5 to 5.5 15 25 -1 A -30 40 70 1.5 1.5 0.4 0.4 70 150 2.5 to 5.5 VDD-1 4.5 to 5.5 3.0 to 5.5 VDD-1.8 VDD-1.8 V 2.5 to 5.5 VDD-1 2.5 to 5.5 2.5 to 5.5 4.5 to 5.5 3.0 to 5.5 2.5 to 5.5 2.5 to 5.5 4.5 to 5.5 3.0 to 5.5 -1 -1 VDD-1 VDD-1 VDD-0.5 VDD-1 VDD-1.8 VDD-1.8 2.5 to 5.5 -1 2.5 to 5.5 2.5 to 5.5 1 1 A 2.5 to 5.5 1 min Specification typ max unit
k
No.A1122-11/19
LC876D16A/08A
Serial I/O Characteristics at Ta = -40C to +85C, VSS1 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter Frequency Low level Input clock pulse width High level pulse width tSCKHA(1) * Continuous data transmission/reception mode Serial clock * See Fig. 6. * (Note 4-1-2) Frequency Low level Output clock pulse width High level pulse width tSCKHA(2) * Continuous data transmission/reception mode * CMOS output selected * See Fig. 6. Data setup time Serial input tsDI(1) SB0(P11), SI0(P11) Data hold time thDI(1) 2.5 to 5.5 Output delay Input clock time tdD0(2) tdD0(1) SO0(P10), SB0(P11) * Continuous data transmission/reception mode * (Note 4-1-3) * Synchronous 8-bit mode * (Note 4-1-3) tdD0(3) Output clock (Note 4-1-3) (1/3)tCYC +0.05 2.5 to 5.5 2.5 to 5.5 0.03 * Must be specified with respect to rising edge of SIOCLK. * See Fig. 6. 2.5 to 5.5 0.03 tSCKH(2) +2tCYC tSCKH(2) 2.5 to 5.5 tSCK(2) tSCKL(2) SCK0(P12) * CMOS output selected * See Fig. 6. 4/3 1/2 tSCK 1/2 tSCKH(2) +(10/3) tCYC tCYC 4 tSCKH(1) 2.5 to 5.5 Symbol tSCK(1) tSCKL(1) Pin/ Remarks SCK0(P12) See Fig. 6. Conditions VDD[V] min 2 1 1 tCYC Specification typ max unit
(1/3)tCYC +0.05 s 1tCYC +0.05
Serial output
2.5 to 5.5
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6.
No.A1122-12/19
LC876D16A/08A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Parameter Frequency Input clock Low level pulse width High level pulse width Frequency Output clock Low level pulse width High level pulse width Data setup time Serial input tsDI(2) SB1(P14), SI1(P14) Data hold time thDI(2) * Must be specified with respect to rising edge of SIOCLK. * See Fig. 6. 2.5 to 5.5 Output delay time Serial output tdD0(4) SO1(P13), SB1(P14) * Must be specified with respect to falling edge of SIOCLK. * Must be specified as the time to the beginning of output state change in open drain output mode. * See Fig. 6. 2.5 to 5.5 (1/3)tCYC +0.05 0.03 2.5 to 5.5 0.03 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) * CMOS output selected * See Fig. 6. 2.5 to 5.5 tSCKH(3) Symbol tSCK(3) tSCKL(3) Pin/ Remarks SCK1(P15) Conditions VDD[V] See Fig. 6. min 2 2.5 to 5.5 1 tCYC 1 2 1/2 tSCK 1/2 Specification typ max unit
Serial clock
s
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
Pulse Input Conditions at Ta = -40C to +85C, VSS1 = 0V
Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) Pin/Remarks INT0(P70), INT1(P71), INT2(P16) INT3(P17) (Noise rejection ratio set to 1/1.) INT3(P17) (Noise rejection ratio set to 1/32.) INT3(P17) (Noise rejection ratio set to 1/128.) RES Reset possible 2.5 to 5.5 200 s * Interrupt acceptable * Events to timer 0 can be input. 2.5 to 5.5 256 * Interrupt acceptable * Events to timer 0 can be input. 2.5 to 5.5 64 * Interrupt acceptable * Events to timer 0 can be input. 2.5 to 5.5 2 tCYC Conditions VDD[V] * Interrupt acceptable * Events to timer 0, 1 can be input. 2.5 to 5.5 1 min Specification typ max unit
No.A1122-13/19
LC876D16A/08A
AD Converter Characteristics at Ta = -40C to +85C, VSS1 = 0V
Parameter Resolution Absolute precision Conversion time tCAD AD conversion time=32xtCYC (ADCR2=0) (Note 6-2) 3.0 to 5.5 AD conversion time=64xtCYC (ADCR2=1) (Note 6-2) 3.0 to 5.5 Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN 4.5 to 5.5 4.5 to 5.5 Symbol N ET Pin/Remarks AN0(P00) to AN7(P07) (Note 6-1) Conditions VDD[V] 3.0 to 5.5 3.0 to 5.5 15.62 (tCYC= 0.488s) 23.52 (tCYC= 0.735s) 18.82 (tCYC= 0.294s) 47.04 (tCYC= 0.735s) 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 -1 VSS min Specification typ 8 1.5 97.92 (tCYC= 3.06s) 97.92 (tCYC= 3.06s) 97.92 (tCYC= 1.53s) 97.92 (tCYC= 1.53s) VDD 1 V A s max unit bit LSB
Note 6-1: Absolute precision not including quantizing error (1/2 LSB). Note 6-2: Conversion time means time from executing AD conversion instruction to loading complete digital value to register.
Consumption Current Characteristics at Ta = -40C to +85C, VSS1 = 0V
Parameter Current dissipation during basic operation (Note 7-1) IDDOP(2) Symbol IDDOP(1) Pin/ Remarks VDD1 =VDD2 =VDD3 Conditions VDD[V] * FmCF=10Hz for ceramic resonator oscillation * System clock: 10MHz * Internal RC oscillation stopped. * 1/1 frequency division ratio * CF1=15MHz for external clock * System clock: CF1 oscillation * Internal RC oscillation stopped. * 1/2 frequency division ratio IDDOP(3) * FmCF=4MHz for ceramic resonator oscillation * System clock: 4MHz * Internal RC oscillation stopped. * 1/1 frequency division ratio IDDOP(4) * FmCF=0Hz (No oscillation) * System clock: RC oscillation * Divider set to 1/2 IDDOP(5) * FsX'tal=32.768kHz for crystal oscillation * System clock: 32.768KHz * Internal RC oscillation stopped. * 1/2 frequency division ratio 2.5 to 4.5 4.5 to 5.5 2.5 to 4.5 0.33 42 24 1.5 220 A 150 4.5 to 5.5 0.48 2.0 3.0 to 4.5 1.9 5.7 3.0 to 4.5 5.0 15 4.5 to 5.5 6.6 20 min Specification typ max unit
4.5 to 5.5 3.0 to 4.5 4.5 to 5.5
8.5 7.5 2.6
25 22 7.8
mA
Note 7-1: The currents of the output transistors and the pull-up MOS transistors are ignored.
Continued on next page.
No.A1122-14/19
LC876D16A/08A
Continued from preceding page.
Parameter Current dissipation HALT mode (Note 7-1) Symbol IDDHALT(1) Pin/ Remarks VDD1 =VDD2 =VDD3 HALT mode * FmCF=10MHz for Ceramic resonator oscillation * System clock: 10MHz * Internal RC oscillation stopped. * Divider: 1/1 IDDHALT(2) HALT mode * CF1=15MHz for external clock * System clock: CF1 oscillation * Internal RC oscillation stopped. * Divider 1/2 IDDHALT(3) HALT mode * FmCF=4MHz for Ceramic resonator oscillation * System clock: 4MHz * Internal RC oscillation stopped. * Divider: 1/1 IDDHALT(4) HALT mode * FmCF=0Hz (When oscillation stops.) * System clock: RC oscillation * Divider: 1/2 IDDHALT(5) HALT mode * FsX'tal=32.768kHz for crystal oscillation * Internal RC oscillation stopped. * System clock: 32.768kHz * Divider: 1/2 Current dissipation HOLD mode Current dissipation Date/time clock HOLD mode IDDHOLD(2) VDD1 IDDHOLD(1) VDD1 HOLD mode * CF1=VDD or open circuit (when using external clock) Date/time clock HOLD mode * CF1=VDD or open circuit (when using external clock) * FsX'tal=32.768kHz for crystal oscillation 2.5 to 4.5 18 55 4.5 to 5.5 35 85 4.5 to 5.5 2.5 to 4.5 0.02 0.01 20 15 2.5 to 4.5 20 60 A 4.5 to 5.5 2.5 to 4.5 4.5 to 5.5 300 210 37 1000 630 95 2.5 to 4.5 0.8 2.4 4.5 to 5.5 1.2 3.6 3.0 to 4.5 2.2 6.6 4.5 to 5.5 3.8 11.4 mA 3.0 to 4.5 1.8 5.4 4.5 to 5.5 2.6 8.4 Conditions VDD[V] min Specification typ max unit
Note 7-1: The currents of the output transistors and the pull-up MOS transistors are ignored.
Characteristics of a Sample Main System Clock Oscillation Circuit
The characteristics in the table bellow is based on the following conditions: 1. Use the standard evaluation board SANYO has provided. 2. Use the peripheral parts with indicated value externally. 3. The peripheral parts value is a recommended value of oscillator manufacturer. Table 1. Main system clock oscillation circuit characteristics using ceramic resonator
Circuit Parameters Frequency Manufacturer Oscillator C1 [pF] 4MHz MURATA CSTCR4M00G53-R0 CSTLS4M00G53-B0 10MHz MURATA CSTCE10M0G52-R0 CSTLS10M0G53095-B0 15 15 10 15 C2 [pF] 15 15 10 15 Rd1 [] 2.2k 2.2k 1k 1k Rf1 [] Open Open Open Open Operating Supply Voltage Range [V] 2.2 to 5.5 2.2 to 5.5 2.8 to 5.5 2.9 to 5.5 Oscillation Sstabilizing Time typ [ms] max [ms] Notes
The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than minimum operating voltage. (Refer to Figure 4)
No.A1122-15/19
LC876D16A/08A
Characteristics of a Sample Subsystem Clock Oscillator Circuit
The characteristics in the table bellow is based on the following conditions: 1. Use the standard evaluation board SANYO has provided. 2. Use the peripheral parts with indicated value externally. 3. The peripheral parts value is a recommended value of oscillator manufacturer Table 2 Subsystem clock oscillation circuit characteristics using crystal oscillator
Circuit Parameters Frequency Manufacturer Oscillator C3 [pF] C4 [pF] Rd2 [] Rf2 [] Operating Supply Voltage Range [V] Oscillation Stabilizing Time typ [s] max [s] Notes
The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the sub-clock oscillation or after releasing the HOLD mode. (Refer to Figure 4) Notes: Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length.
CF1
CF2
XT1
XT2
Rf1
Rd1
Rf2
Rd2
C1 CF
C2
C3 X'tal
C4
Figure 1 Ceramic Oscillation Circuit
Figure 2 Crystal Oscillation Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A1122-16/19
LC876D16A/08A
VDD VDD limit Power supply Reset time 0V
RES
Internal RC oscillation tmsCF
CF1, CF2 tmsX'tal
XT1, XT2
Operating mode
Unfixed
Reset
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset signal
Without HOLD reset signal
HOLD reset signal VALID
Internal RC oscillation tmsCF
CF1,CF2 tmsX'tal
XT1, XT2
Operating mode
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Time
No.A1122-17/19
LC876D16A/08A
VDD
RRES
Note: Set CRES, RRES values such that reset time exceeds 200s.
RES CRES
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7 Data RAM transmission period (only SIO0)
DO8
tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: Data RAM transmission period (only SIO0) tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA thDI tSCKH
Figure 6 Serial I/O Waveform
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A1122-18/19
LC876D16A/08A
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above.
This catalog provides information as of February, 2008. Specifications and information herein are subject to change without notice.
PS No.A1122-19/19

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